| Presentation | 2005-12-02 A Cycle Budgeting Method for Tasks and Bus Transfers of Bus Systems Using Scenarios Seiji YAMAGUCHI, Tadaaki TANIMOTO, Akio NAKATA, Teruo HIGASHINO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each task module of the bus system while satisfying the given end-to-end real-time constraint of the entire system such as throughput and/or latency constraints. In this paper, we define a scenario as execution sequences of tasks and bus transfers executed in a bus system. Then we propose a method to derive real-time constraints for each task and bus transfer from a given bus system configuration (including bus topology) and a scenario. In deriving the real-time constraints, we consider operation strengths of tasks, the amount of bus transfers, and bus scheduling policies (either fixed priority or round robin). We show that our method is effective for a MPEG2 decoder bus system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Bus systems / Real-time systems / Pipelined processing / Multimedia processing / Cycle budgeting |
| Paper # | VLD2005-80,ICD2005-175,DC2005-57 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2005/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Cycle Budgeting Method for Tasks and Bus Transfers of Bus Systems Using Scenarios |
| Sub Title (in English) | |
| Keyword(1) | Bus systems |
| Keyword(2) | Real-time systems |
| Keyword(3) | Pipelined processing |
| Keyword(4) | Multimedia processing |
| Keyword(5) | Cycle budgeting |
| 1st Author's Name | Seiji YAMAGUCHI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Tadaaki TANIMOTO |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Akio NAKATA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 4th Author's Name | Teruo HIGASHINO |
| 4th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2005-12-02 |
| Paper # | VLD2005-80,ICD2005-175,DC2005-57 |
| Volume (vol) | vol.105 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |