| Presentation | 2005-12-02 A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a broadside test generation method for transition faults in partial scan circuits. In order to generate broadside transition tests for a given partial scan circuit whose kernel circuit is acyclic, this method transforms the kernel circuit into some combinational circuits called broadside test generation models. These models are constructed by using a time-expansion model of the kernel circuit. All the broadside transition tests are generated by performing constrained stuck-at test generation on the broadside test generation models. This method is effective in terms of over-testing as well as area overhead compared with enhanced scan testing and broadside testing based on full scan technique. Experimental results show that the proposed method can alleviate the over-testing issue in reasonable test generation time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | transition fault / broadside test / broadside test generation model / constrained stuck-at test generation / over-testing |
| Paper # | VLD2005-77,ICD2005-172,DC2005-54 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits |
| Sub Title (in English) | |
| Keyword(1) | transition fault |
| Keyword(2) | broadside test |
| Keyword(3) | broadside test generation model |
| Keyword(4) | constrained stuck-at test generation |
| Keyword(5) | over-testing |
| 1st Author's Name | Tsuyoshi IWAGAKI |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2005-12-02 |
| Paper # | VLD2005-77,ICD2005-172,DC2005-54 |
| Volume (vol) | vol.105 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |