Presentation | 2005-12-01 Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect Yoichi YUYAMA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a bit error rate modeling methodology for error detection/correction encoding of on-chip global interconnect. We classify "Deterministic Noise" and "Probablistic Noise" that are mixed up by conventional method. Our method enables realistic noise and bit error rate modeling. We compare bit error rate estimated by conventional and our proposed method, both are 100 times different. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | On-Chip Global Interconnect / Bit Error Rate Modeling |
Paper # | VLD2005-73,ICD2005-168,DC2005-50 |
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Committee | ICD |
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Conference Date | 2005/11/24(1days) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect |
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Keyword(1) | On-Chip Global Interconnect |
Keyword(2) | Bit Error Rate Modeling |
1st Author's Name | Yoichi YUYAMA |
1st Author's Affiliation | Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University() |
2nd Author's Name | Kazutoshi KOBAYASHI |
2nd Author's Affiliation | Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University |
3rd Author's Name | Hidetoshi ONODERA |
3rd Author's Affiliation | Dept. of Comm. and Comp. Eng., Graduate School of Informatics, Kyoto University |
Date | 2005-12-01 |
Paper # | VLD2005-73,ICD2005-168,DC2005-50 |
Volume (vol) | vol.105 |
Number (no) | 445 |
Page | pp.pp.- |
#Pages | 6 |
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