Presentation | 2005-11-10 On the Complexity of Fault Testing for Reversible Circuits Shigeru ITO, Yusuke ITO, Satoshi TAYU, Shuichi UENO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on a set of wires of a reversible circuit. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Fault testing / NP-complete / reversible circuit |
Paper # | CAS2005-51,CST2005-20 |
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Conference Information | |
Committee | CAS |
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Conference Date | 2005/11/3(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Circuits and Systems (CAS) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | On the Complexity of Fault Testing for Reversible Circuits |
Sub Title (in English) | |
Keyword(1) | Fault testing |
Keyword(2) | NP-complete |
Keyword(3) | reversible circuit |
1st Author's Name | Shigeru ITO |
1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
2nd Author's Name | Yusuke ITO |
2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
3rd Author's Name | Satoshi TAYU |
3rd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
4th Author's Name | Shuichi UENO |
4th Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
Date | 2005-11-10 |
Paper # | CAS2005-51,CST2005-20 |
Volume (vol) | vol.105 |
Number (no) | 387 |
Page | pp.pp.- |
#Pages | 4 |
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