Presentation	2005/11/12 Hardware implementation of self organizing map with DPLL Hiroomi HIKAWA,
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Abstract(in English)	The self-organizing map (SOM) has found applicability in a wide range of application areas. This paper proposes a new SOM hardware with digital phase-locked loop (DPLL) The system uses the DPLL as a computing element because the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.
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Keyword(in English)	Self-organizing map / phase modulation / DPLL / pulse signal / FPGA
Paper #	NC2005-73
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Conference Information
Committee	NC
Conference Date	2005/11/12(1days)
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Paper Information
Registration To	Neurocomputing (NC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Hardware implementation of self organizing map with DPLL
Sub Title (in English)
Keyword(1)	Self-organizing map
Keyword(2)	phase modulation
Keyword(3)	DPLL
Keyword(4)	pulse signal
Keyword(5)	FPGA
1st Author's Name	Hiroomi HIKAWA
1st Author's Affiliation	Oita University()
Date	2005/11/12
Paper #	NC2005-73
Volume (vol)	vol.105
Number (no)	419
Page	pp.pp.-
#Pages	6
Date of Issue