| Presentation | 2005/11/12 Precisely-timed synchronization among spiking neuron circuits on silicon neural networks : Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP lerning units Tetsuya HIROSE, Alexandre SCHMID, Tetsuya ASAI, Yusuf Leblebici, Yoshihito AMEMIYA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A neural network exhibiting precisely-timed synchronization under noisy environment with depressing synapses has been proposed in the literature [4]. In this report, we construct a recurrent neural network by using silicon neuron circuits [5] and depressing synapse circuits [6] that have already been developed by the authors, and examine that timing precision among silicon neurons by numerical simulations. Consequently, timing jitter among the neurons was significantly improved by depressing synapse circuits, as compared with non-depressed one. Moreover, a simple analog STDP circuit is designed for constructing a neural network that exhibits robust synchronization under noisy environment. We confirmed its desired operations by numerical simulations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | neuromophic VLSI / depressing synapse / spiking neurons / recurrent neural network / STDP |
| Paper # | NC2005-72 |
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| Committee | NC |
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| Conference Date | 2005/11/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Neurocomputing (NC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Precisely-timed synchronization among spiking neuron circuits on silicon neural networks : Analog implementation of integrate-and-fire neurons, depressing synapses, and STDP lerning units |
| Sub Title (in English) | |
| Keyword(1) | neuromophic VLSI |
| Keyword(2) | depressing synapse |
| Keyword(3) | spiking neurons |
| Keyword(4) | recurrent neural network |
| Keyword(5) | STDP |
| 1st Author's Name | Tetsuya HIROSE |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University() |
| 2nd Author's Name | Alexandre SCHMID |
| 2nd Author's Affiliation | Microelectronic Systems Laboratory, Swiss Federal Institute of Technology(EPFL) |
| 3rd Author's Name | Tetsuya ASAI |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| 4th Author's Name | Yusuf Leblebici |
| 4th Author's Affiliation | Microelectronic Systems Laboratory, Swiss Federal Institute of Technology(EPFL) |
| 5th Author's Name | Yoshihito AMEMIYA |
| 5th Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| Date | 2005/11/12 |
| Paper # | NC2005-72 |
| Volume (vol) | vol.105 |
| Number (no) | 419 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |