Presentation	2005-12-02 Evaluation of Reconfigurable and Highly Functional Memory Controller Toshiharu IMAI, Kiyofumi TANAKA,
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Abstract(in English)	In this paper, we propose a method of supporting fast execution for large amount of data, by equipping a memory controller (MC) with ability to reduce memory access latency and alleviate a gap between CPU and memory speed by cooperating with reconfigurable FIFO buffer in CPU cache, and reconfigurable functional unit. Then, we evaluate the proposed MC which reconfigurable functional unit is MAC which is a feature of DSP using for FIR/IIR filter.
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Keyword(in English)	Memory controller (MC) / Filtering / Reconfigurable
Paper #	RECONF2005-75
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Conference Information
Committee	RECONF
Conference Date	2005/11/25(1days)
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Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Evaluation of Reconfigurable and Highly Functional Memory Controller
Sub Title (in English)
Keyword(1)	Memory controller (MC)
Keyword(2)	Filtering
Keyword(3)	Reconfigurable
1st Author's Name	Toshiharu IMAI
1st Author's Affiliation	School of Information Science, Japan Advanced Institute of Science and Technology()
2nd Author's Name	Kiyofumi TANAKA
2nd Author's Affiliation	School of Information Science, Japan Advanced Institute of Science and Technology
Date	2005-12-02
Paper #	RECONF2005-75
Volume (vol)	vol.105
Number (no)	452
Page	pp.pp.-
#Pages	6
Date of Issue