Presentation 2005-12-02
Online FPGA Placement under I/O Timing Constraints
Mitsuru TOMONO, Masaki NAKANISHI, Shigeru YAMASHITA, Katsumasa WATANABE,
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Abstract(in English) In recent years, FPGAs are effectively-utilized in various fields. Among them, devices with partial reconfiguration are appearing. Partially reconfigurable FPGAs have an ability to map and execute several tasks simultaneously and, that is, hardware multitasking becomes available on them. In such systems, management of the FPGA resources is necessary. Recently, some works of the online FPGA placement method are done. However, existing methods ignore tasks' I/O timing constraints and data communications. In this paper, we propose a new online FPGA placement method. Our method makes each free area have I/O routing information and the placer module uses this information for placement.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Online Placement / Partially Reconfigurable FPGA / Reconfigurable Computing / Resource Management / I/O timing constraints
Paper # RECONF2005-73
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Committee RECONF
Conference Date 2005/11/25(1days)
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Registration To Reconfigurable Systems (RECONF)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Online FPGA Placement under I/O Timing Constraints
Sub Title (in English)
Keyword(1) Online Placement
Keyword(2) Partially Reconfigurable FPGA
Keyword(3) Reconfigurable Computing
Keyword(4) Resource Management
Keyword(5) I/O timing constraints
1st Author's Name Mitsuru TOMONO
1st Author's Affiliation Nara Institute of Science and Technology()
2nd Author's Name Masaki NAKANISHI
2nd Author's Affiliation Nara Institute of Science and Technology
3rd Author's Name Shigeru YAMASHITA
3rd Author's Affiliation Nara Institute of Science and Technology
4th Author's Name Katsumasa WATANABE
4th Author's Affiliation Nara Institute of Science and Technology
Date 2005-12-02
Paper # RECONF2005-73
Volume (vol) vol.105
Number (no) 452
Page pp.pp.-
#Pages 6
Date of Issue