| Presentation | 2005-12-01 A Study of the High-Speed Reconfigurable System for Object Recognition Hiroshi KADOTA, Shingo KASAKI, Akiyoshi WAKATANI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A high-speed reconfigurable system for the real-time object recognition in the motion pictures is proposed. The object-recognition engine in the system has local memories, data-transfer subsystems and parallel arithmetic subsystems in it. The data transfer subsystem, which consists of two types of buffers and an interconnection network, can supply two-dimensionally sampled pixel data to the parallel arithmetic subsystem rapidly. The parallel arithmetic subsystem, which consists of 1500 arithmetic units with an 8/16 bit MAC unit, a shifter and an 80-entry code buffer, has a reconfigurable structure to realize high-speed parallel operations for several object-recognition procedures. A face-detection algorithm by template matching, which we have proposed previously, is parallelized and implemented onto the engine, and its processing time is estimated for the performance evaluation. Consequently, it is found that face detection in the 720×480 picture could be carried out within 12ms, and real-time face detection in the 30frames/s motion pictures would be possible by using this reconfigurable system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable System / Multi-stage Connection Network / Object Recognition / Parallel-processing System |
| Paper # | RECONF2005-71 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2005/11/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of the High-Speed Reconfigurable System for Object Recognition |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable System |
| Keyword(2) | Multi-stage Connection Network |
| Keyword(3) | Object Recognition |
| Keyword(4) | Parallel-processing System |
| 1st Author's Name | Hiroshi KADOTA |
| 1st Author's Affiliation | Faculty of Design, Kyushu University() |
| 2nd Author's Name | Shingo KASAKI |
| 2nd Author's Affiliation | Faculty of Design, Kyushu University |
| 3rd Author's Name | Akiyoshi WAKATANI |
| 3rd Author's Affiliation | Faculty of Science and Engineering, Konan University |
| Date | 2005-12-01 |
| Paper # | RECONF2005-71 |
| Volume (vol) | vol.105 |
| Number (no) | 451 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |