Presentation 2005-12-01
Mapping of FFT onto Dynamically Reconfigurable Processor FE-GA
Makoto SATOH, Hiroshi TANAKA, Takanobu TSUNODA, Masashi TAKADA, Yohei AKITA, Masaki ITO,
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Abstract(in English) Dynamically reconfigurable processors are getting popular in the fields such as wireless LAN, Audio, and Video processing, that need high performance and lots of new protocols. We have been researching such a processor, FE-GA, which is aiming at high performance per area. This paper proposes a new data placing algorithm for Fast Fourier Transform (FFT), its mapping onto FE-GA, and a new performance evaluation index, Utilization Ratio of Principal calculation unit (URP); and evaluates our mapping using it. As a result, we found that URP for multiplication is 96% for 2048-point FFT and our architecture achieves a high performance per area for FFT.
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Keyword(in English) Dynamically Reconfigurable Processor / FFT / Mapping / Utilization Ratio
Paper # RECONF2005-68
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Committee RECONF
Conference Date 2005/11/24(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Mapping of FFT onto Dynamically Reconfigurable Processor FE-GA
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) FFT
Keyword(3) Mapping
Keyword(4) Utilization Ratio
1st Author's Name Makoto SATOH
1st Author's Affiliation Systems Development Lab., Hitachi, Ltd.()
2nd Author's Name Hiroshi TANAKA
2nd Author's Affiliation Central Research Lab., Hitachi, Ltd.
3rd Author's Name Takanobu TSUNODA
3rd Author's Affiliation Central Research Lab., Hitachi, Ltd.
4th Author's Name Masashi TAKADA
4th Author's Affiliation Central Research Lab., Hitachi, Ltd.
5th Author's Name Yohei AKITA
5th Author's Affiliation Central Research Lab., Hitachi, Ltd.
6th Author's Name Masaki ITO
6th Author's Affiliation Central Research Lab., Hitachi, Ltd.
Date 2005-12-01
Paper # RECONF2005-68
Volume (vol) vol.105
Number (no) 451
Page pp.pp.-
#Pages 6
Date of Issue