Presentation 2005-12-01
Design of an Application Layer Processing Engine using Dynamic Reconfiguration
Yutaka SUGAWARA, Mary INABA, Kei HIRAKI,
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Abstract(in English) In this paper, we propose two techniques to reduce the performance overhead of reconfiguration when multiple application layer tasks are processed on an FPGA. First, we propose module-versioning method. In this method, the system selects an optimal module for each task among multiple modules that differ in the throughput and size. Secondly, we propose software cooperation method. In this method, tasks are processed using software rather than hardware when the required throughput is not high, or the corresponding FPGA module has not been programmed yet. Using these methods, the reconfiguration frequency is reduced, and a part of overhead for each reconfiguration can be hidden.
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Keyword(in English) FPGA / application layer / runtime reconfiguration
Paper # RECONF2005-60
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Committee RECONF
Conference Date 2005/11/24(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of an Application Layer Processing Engine using Dynamic Reconfiguration
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) application layer
Keyword(3) runtime reconfiguration
1st Author's Name Yutaka SUGAWARA
1st Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo()
2nd Author's Name Mary INABA
2nd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo
3rd Author's Name Kei HIRAKI
3rd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo
Date 2005-12-01
Paper # RECONF2005-60
Volume (vol) vol.105
Number (no) 451
Page pp.pp.-
#Pages 6
Date of Issue