Presentation 2005-11-30
A New Design Method for Implementing Real-Time Embedded Systems on Dynamically Reconfigurable Processors
Ryo NAKAHASHI, Tomoya KITANI, Keiichi YASUMOTO, Akio NAKATA, Teruo HIGASHINO,
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Abstract(in English) The dynamically reconfigurable processor (DRP, hereafter) has multiple different circuit patterns called contexts which can dynamically be switched during execution. Recently, there are many research efforts to use DRP for reduction of circuit sizes, power consumption and so on. In this paper, we propose a method to divide a given specification of a real-time embedded system to multiple sub-specifications so that the sub-specifications are executed on multiple contexts of a DRP, respectively. Here, the time constraints in the original specification must be satisfied in the set of sub-specifications and the sum of waiting time at context switching must be minimized. This problem is NP-hard. In this paper, we developed a heuristic algorithm to solve this problem and applied our technique to a MPEG video decoding system.
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Keyword(in English) reconfigurable processor / dynamic reconfigurable / multicontext partitioning / timing constraint / heuristic algorithm
Paper # RECONF2005-58
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Conference Information
Committee RECONF
Conference Date 2005/11/23(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A New Design Method for Implementing Real-Time Embedded Systems on Dynamically Reconfigurable Processors
Sub Title (in English)
Keyword(1) reconfigurable processor
Keyword(2) dynamic reconfigurable
Keyword(3) multicontext partitioning
Keyword(4) timing constraint
Keyword(5) heuristic algorithm
1st Author's Name Ryo NAKAHASHI
1st Author's Affiliation Graduate School of Information Science and Technology, Osaka University()
2nd Author's Name Tomoya KITANI
2nd Author's Affiliation Graduate School of Information Science and Technology, Osaka University
3rd Author's Name Keiichi YASUMOTO
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
4th Author's Name Akio NAKATA
4th Author's Affiliation Graduate School of Information Science and Technology, Osaka University
5th Author's Name Teruo HIGASHINO
5th Author's Affiliation Graduate School of Information Science and Technology, Osaka University
Date 2005-11-30
Paper # RECONF2005-58
Volume (vol) vol.105
Number (no) 450
Page pp.pp.-
#Pages 6
Date of Issue