Presentation 2005-11-30
Implementation of Basic Function Blocks for Variable Grain Logic Cell
Naoto HAMABE, Hideaki NAKAYAMA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,
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Abstract(in English) We can devide commercially avairable reconfigurable logic devices into two categories by processing data size, one is a coarse-grain architecture and the another is fine-grain architecture. The coarse-grain architecture excels in arithmetic operation, and the fine-grain architecture excels in implementation of versatile logical circuit. Since each application contains arithmetic operation at various rates, we cannot implement these in above architectures efficiently. As a solution for this problem, we propose variable grain logic cell. It can operate both arithmetic operations between coarse-grain and fine-grain efficiently. This paper describes implementation results of function block in variable grain logic cell. Hereby, the number of transistors was reduced by 50% compared to LUT-based FPGA.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) reconfigurable logic device / coarse grain / fine grain
Paper # RECONF2005-54
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Committee RECONF
Conference Date 2005/11/23(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of Basic Function Blocks for Variable Grain Logic Cell
Sub Title (in English)
Keyword(1) reconfigurable logic device
Keyword(2) coarse grain
Keyword(3) fine grain
1st Author's Name Naoto HAMABE
1st Author's Affiliation Department of Mathmatics and Computers Science, Graduate School of Science and Technology()
2nd Author's Name Hideaki NAKAYAMA
2nd Author's Affiliation Department of Mathmatics and Computers Science, Graduate School of Science and Technology
3rd Author's Name Motoki AMAGASAKI
3rd Author's Affiliation Department of Mathmatics and Computers Science, Graduate School of Science and Technology
4th Author's Name Masahiro IIDA
4th Author's Affiliation Department of Mathmatics and Computers Science, Faculty of engineering, Kumamoto University
5th Author's Name Toshinori SUEYOSHI
5th Author's Affiliation Department of Mathmatics and Computers Science, Faculty of engineering, Kumamoto University
Date 2005-11-30
Paper # RECONF2005-54
Volume (vol) vol.105
Number (no) 450
Page pp.pp.-
#Pages 6
Date of Issue