Presentation 2005-12-01
Comparison of power consumption by form of adders
Takayuki MINAKUCHI, Shintaro MIMOTO, Masayoshi TACHIBANA,
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Abstract(in English) We reported "Comparison of power consumption, area and speed by form of adders" at the VLSI design technical research meeting in May. Because we examined behavior of power consumption when we changed a simulation pattern in simulation of power consumption, we report this. In this research, we researched the following two points. The 1st points, when we changed the number of patterns simulation with 100 times, 1,000 times, 10,000 times, we examined whether a big change occurred in power consumption. The 2nd points, we examined a change of power consumption when we changed input arrival time each bit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) adder / power consumption / comparison / the number of times / time
Paper # VLD2005-70,ICD2005-165,DC2005-47
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Committee DC
Conference Date 2005/11/24(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Comparison of power consumption by form of adders
Sub Title (in English)
Keyword(1) adder
Keyword(2) power consumption
Keyword(3) comparison
Keyword(4) the number of times
Keyword(5) time
1st Author's Name Takayuki MINAKUCHI
1st Author's Affiliation Electronic and Photonic Systems Engineering Cource, Kochi University of Technology()
2nd Author's Name Shintaro MIMOTO
2nd Author's Affiliation Electronic and Photonic Systems Engineering Cource, Kochi University of Technology
3rd Author's Name Masayoshi TACHIBANA
3rd Author's Affiliation Electronic and Photonic Systems Engineering Cource, Kochi University of Technology
Date 2005-12-01
Paper # VLD2005-70,ICD2005-165,DC2005-47
Volume (vol) vol.105
Number (no) 448
Page pp.pp.-
#Pages 5
Date of Issue