| Presentation | 2005-11-30 Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation Kouichi WATANABE, Masashi IMAI, Masaaki KONDO, Hiroshi NAKAMURA, Takashi NANYA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the VLSI technology advances, delay variations will become more serious. Delay insensitive asynchronous dual-rail circuits tolerate any delay variation, but its energy consumption is more than twice of the single-rail circuit. However, in functional units, a significant number of input bits may not change from the previous input. Thus, we propose a method called unflip-bits control. We evaluate the energy consumption and performance penalty for the method using simulators, and compare the method with conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed unflip-bits control is quite effective method of reducing the energy consumption and performance penalty of the asynchronous dual-rail circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay Variation / Dual-rail Asynchronous Circuit / Functional Unit / Unflip-Bit Control |
| Paper # | VLD2005-60,ICD2005-155,DC2005-37 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation |
| Sub Title (in English) | |
| Keyword(1) | Delay Variation |
| Keyword(2) | Dual-rail Asynchronous Circuit |
| Keyword(3) | Functional Unit |
| Keyword(4) | Unflip-Bit Control |
| 1st Author's Name | Kouichi WATANABE |
| 1st Author's Affiliation | Research Center for Advanced Science and Technology, The University of Tokyo() |
| 2nd Author's Name | Masashi IMAI |
| 2nd Author's Affiliation | Research Center for Advanced Science and Technology, The University of Tokyo |
| 3rd Author's Name | Masaaki KONDO |
| 3rd Author's Affiliation | Research Center for Advanced Science and Technology, The University of Tokyo |
| 4th Author's Name | Hiroshi NAKAMURA |
| 4th Author's Affiliation | Research Center for Advanced Science and Technology, The University of Tokyo |
| 5th Author's Name | Takashi NANYA |
| 5th Author's Affiliation | Research Center for Advanced Science and Technology, The University of Tokyo |
| Date | 2005-11-30 |
| Paper # | VLD2005-60,ICD2005-155,DC2005-37 |
| Volume (vol) | vol.105 |
| Number (no) | 447 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |