Presentation 2005-11-30
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Masao MORIMOTO, Makoto NAGATA, Kazuo TAKI,
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Abstract(in English) This paper proposes a logic synthesis technique for asymmetric slope differential dynamic logic (ASDDL) circuits. The technique utilizes a commercially available logic synthesis tool that has been well established for static CMOS logic design, where an intermediate library is devised for logic synthesis likely as static CMOS, and then a resulting synthesized circuit is translated automatically into ASDDL implementation at the gate-level logic schematic level as well as at the physical-layout level. A design example of an ASDDL 16-bit multiplier synthesized in a 0.18-μm CMOS technology shows an operation delay time of 1.82nsec, which is a 32% improvement over a static CMOS design with a static logic standard-cell library that is finely tuned for energy-delay products. Design time for an ASDDL based dynamic digital circuit is sharply shortened by the proposed logic synthesis technique, and comparable with a static CMOS design.
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Keyword(in English) logic synthesis / ASDDL / asymmetric slope / high-speed operation
Paper # VLD2005-58,ICD2005-153,DC2005-35
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Committee DC
Conference Date 2005/11/23(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
Sub Title (in English)
Keyword(1) logic synthesis
Keyword(2) ASDDL
Keyword(3) asymmetric slope
Keyword(4) high-speed operation
1st Author's Name Masao MORIMOTO
1st Author's Affiliation Graduate School of Science and Technology, Department of Computer and Systems Engineering, Kobe University()
2nd Author's Name Makoto NAGATA
2nd Author's Affiliation Graduate School of Science and Technology, Department of Computer and Systems Engineering, Kobe University
3rd Author's Name Kazuo TAKI
3rd Author's Affiliation AIL Co., Ltd.
Date 2005-11-30
Paper # VLD2005-58,ICD2005-153,DC2005-35
Volume (vol) vol.105
Number (no) 447
Page pp.pp.-
#Pages 6
Date of Issue