| Presentation | 2005-11-30 40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS technology Kouichi Kanda, Daisuke Yamazaki, Takuji Yamamoto, Minoru Horinaka, Junji Ogawa, Hirotaka Tamura, Hiroyuki Onodera, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a 1.2V, 40Gb/s, 4:1 MUX and 1:4 DEMUX designed in 90nm standard CMOS technology, mainly focusing on three design challenges to meet the speed requirement. First, optimization of peaking inductors for 40Gb/s tapered output buffer is explained using effective frequency response analysis. Secondly, circuit topologies of high-speed latch and selector circuits suitable for low-voltage operation are presented. Finally, precise high-frequency device models based on the measured s-parameters up to 40GHz are described. The MUX and DEMUX operate off a single 1.2V supply and consume 110 and 52mA, respectively. Experimental results showed a clear eye opening at a data rate of 40Gb/s. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 40Gb/s / MUX / DEMUX / 90nm CMOS / inductor peaking |
| Paper # | VLD2005-55,ICD2005-150,DC2005-32 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS technology |
| Sub Title (in English) | |
| Keyword(1) | 40Gb/s |
| Keyword(2) | MUX |
| Keyword(3) | DEMUX |
| Keyword(4) | 90nm CMOS |
| Keyword(5) | inductor peaking |
| 1st Author's Name | Kouichi Kanda |
| 1st Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD.() |
| 2nd Author's Name | Daisuke Yamazaki |
| 2nd Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 3rd Author's Name | Takuji Yamamoto |
| 3rd Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 4th Author's Name | Minoru Horinaka |
| 4th Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 5th Author's Name | Junji Ogawa |
| 5th Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 6th Author's Name | Hirotaka Tamura |
| 6th Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| 7th Author's Name | Hiroyuki Onodera |
| 7th Author's Affiliation | System LSI Development Laboratories, Fujitsu Laboratories LTD. |
| Date | 2005-11-30 |
| Paper # | VLD2005-55,ICD2005-150,DC2005-32 |
| Volume (vol) | vol.105 |
| Number (no) | 447 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |