| Presentation | 2005-11-30 Layout CAD and DFM : Beginning and Maturity Takashi Mitsuhashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The auther had an opportunity to be engaged in development of VLSI layout design automation, and automation of design verification, almost 30 years in Toshiba Corp. Now, the auther is involved in development of CAD for DFM (Design for Manufacturing) in Cadence Japan. This paper describes some experiences on those developments, and personal observations related to lifecyle of the technologies and experiences of the research theme selection that auther did. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLSI design / Design automation / Layout design / Design verification / Lifecycle of technologies |
| Paper # | VLD2005-54,ICD2005-149,DC2005-31 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Layout CAD and DFM : Beginning and Maturity |
| Sub Title (in English) | |
| Keyword(1) | VLSI design |
| Keyword(2) | Design automation |
| Keyword(3) | Layout design |
| Keyword(4) | Design verification |
| Keyword(5) | Lifecycle of technologies |
| 1st Author's Name | Takashi Mitsuhashi |
| 1st Author's Affiliation | DFM R&D Japan, Cadence Design Systems() |
| Date | 2005-11-30 |
| Paper # | VLD2005-54,ICD2005-149,DC2005-31 |
| Volume (vol) | vol.105 |
| Number (no) | 447 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |