Presentation 2005-10-21
A study for power and speed tradeoff estimation from behavioral hardware model
Noriyuki Inoue, Katsuhiro Oshikawa, Tomonori Izumi, Masahiro Fukui,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Due to rapid growth of the scale of systems, it becomes a very important task to plan the design strategy based on the power estimation in the early design stage. Power analysis in higher abstraction level is required. Based on a control data flow graph, the authors have developed a structured tradeoff model of power and speed of a given function and a method to obtain the model. This paper gives a fundamental evaluation through a prototype system and discusses its usefulness and future works.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) high-level synthesis / high-level estimation / power estimation / tradeoff analysis
Paper # SIP2005-126,ICD2005-145,IE2005-90
Date of Issue

Conference Information
Committee IE
Conference Date 2005/10/14(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Image Engineering (IE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study for power and speed tradeoff estimation from behavioral hardware model
Sub Title (in English)
Keyword(1) high-level synthesis
Keyword(2) high-level estimation
Keyword(3) power estimation
Keyword(4) tradeoff analysis
1st Author's Name Noriyuki Inoue
1st Author's Affiliation Department of Information Science and Systems Engineering, Ritsumeikan University()
2nd Author's Name Katsuhiro Oshikawa
2nd Author's Affiliation Department of Information Science and Systems Engineering, Ritsumeikan University
3rd Author's Name Tomonori Izumi
3rd Author's Affiliation Department of VLSI System Design, Ritsumeikan University
4th Author's Name Masahiro Fukui
4th Author's Affiliation Department of VLSI System Design, Ritsumeikan University
Date 2005-10-21
Paper # SIP2005-126,ICD2005-145,IE2005-90
Volume (vol) vol.105
Number (no) 354
Page pp.pp.-
#Pages 6
Date of Issue