Presentation | 2005-10-21 Compaction of Arithmetic Unit with Bit-Level-Parallelism Jubei TADA, Ryusuke EGAWA, Gensuke GOTO, Tadao NAKAMURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Aiming at reducing power consumption of VLSIs, we propose a fast and compact arithmetic unit. The arithmetic unit reduces static power consumption by the compaction or the circuit scale. To realize that compaction of the arithmetic unit, we exploit bit level parallelism of arithmetic operation, and also, our approach keeps the throughput and saves a dynamic power consumption employing advanced pipelining technique. The simulation results show a high validity of our proposal on VLSI design in deep submicron era. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Low-power / Arithmetic Unit / Wave-Pipelining |
Paper # | SIP2005-120,ICD2005-139,IE2005-84 |
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Committee | ICD |
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Conference Date | 2005/10/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Compaction of Arithmetic Unit with Bit-Level-Parallelism |
Sub Title (in English) | |
Keyword(1) | Low-power |
Keyword(2) | Arithmetic Unit |
Keyword(3) | Wave-Pipelining |
1st Author's Name | Jubei TADA |
1st Author's Affiliation | Faculty of Engineering, Yamagata University() |
2nd Author's Name | Ryusuke EGAWA |
2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
3rd Author's Name | Gensuke GOTO |
3rd Author's Affiliation | Faculty of Engineering, Yamagata University |
4th Author's Name | Tadao NAKAMURA |
4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
Date | 2005-10-21 |
Paper # | SIP2005-120,ICD2005-139,IE2005-84 |
Volume (vol) | vol.105 |
Number (no) | 352 |
Page | pp.pp.- |
#Pages | 5 |
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