Presentation 2005-10-20
A 333MHz Random Cycle DRAM Using the Floating Body Cell
Kosuke HATSUDA, Katsuyuki FUJITA, Takashi OHSAWA,
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Abstract(in English) A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and an optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.
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Keyword(in English) SOI / Capacitor-less DRAM / FBC / Gain Cell / Embedded Memory
Paper # SIP2005-114,ICD2005-133,IE2005-78
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Conference Date 2005/10/13(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 333MHz Random Cycle DRAM Using the Floating Body Cell
Sub Title (in English)
Keyword(1) SOI
Keyword(2) Capacitor-less DRAM
Keyword(3) FBC
Keyword(4) Gain Cell
Keyword(5) Embedded Memory
1st Author's Name Kosuke HATSUDA
1st Author's Affiliation SoC Research and Development Center, Toshiba Corp. Semiconductor Company()
2nd Author's Name Katsuyuki FUJITA
2nd Author's Affiliation SoC Research and Development Center, Toshiba Corp. Semiconductor Company
3rd Author's Name Takashi OHSAWA
3rd Author's Affiliation SoC Research and Development Center, Toshiba Corp. Semiconductor Company
Date 2005-10-20
Paper # SIP2005-114,ICD2005-133,IE2005-78
Volume (vol) vol.105
Number (no) 351
Page pp.pp.-
#Pages 6
Date of Issue