Presentation	2005-10-20 DFT Techniques for Memory Macro with Built-in ECC Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama,
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Abstract(in English)	DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.
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Keyword(in English)	ECC / DFT / SRAM / hamming code matrix
Paper #	SIP2005-111,ICD2005-130,IE2005-75
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Conference Information
Committee	ICD
Conference Date	2005/10/13(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	DFT Techniques for Memory Macro with Built-in ECC
Sub Title (in English)
Keyword(1)	ECC
Keyword(2)	DFT
Keyword(3)	SRAM
Keyword(4)	hamming code matrix
1st Author's Name	Keiichi Kushida
1st Author's Affiliation	SoC Research & Development Center, Toshiba Corporation()
2nd Author's Name	Nobuaki Otsuka
2nd Author's Affiliation	SoC Research & Development Center, Toshiba Corporation
3rd Author's Name	Osamu Hirabayashi
3rd Author's Affiliation	SoC Research & Development Center, Toshiba Corporation
4th Author's Name	Yasuhisa Takeyama
4th Author's Affiliation	SoC Research & Development Center, Toshiba Corporation
Date	2005-10-20
Paper #	SIP2005-111,ICD2005-130,IE2005-75
Volume (vol)	vol.105
Number (no)	351
Page	pp.pp.-
#Pages	6
Date of Issue