Presentation	2005-10-20 A Memory Controller that Reduces Latency of Cached SDRAM Seiji MIURA, Satoru AKIYAMA,
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Abstract(in English)	The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These two schemes cooperatively control cached SDRAM to reduce its latency. Testing of the controller using benchmark programs demonstrated that latency was reduced 25% and execution time was reduced 13% compare to those of a sense-amplifier cache controller for standard SDRAM. The proposed controller requires 9.3Kgates at a supply voltage of 1.8V and an operating frequency of 133MHz.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	cached SDRAM / memory controller / latency / dummy-cache control scheme
Paper #	SIP2005-110,ICD2005-129,IE2005-74
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Conference Information
Committee	ICD
Conference Date	2005/10/13(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Memory Controller that Reduces Latency of Cached SDRAM
Sub Title (in English)
Keyword(1)	cached SDRAM
Keyword(2)	memory controller
Keyword(3)	latency
Keyword(4)	dummy-cache control scheme
1st Author's Name	Seiji MIURA
1st Author's Affiliation	Hitachi, Ltd. Central Research Laboratory()
2nd Author's Name	Satoru AKIYAMA
2nd Author's Affiliation	Hitachi, Ltd. Central Research Laboratory
Date	2005-10-20
Paper #	SIP2005-110,ICD2005-129,IE2005-74
Volume (vol)	vol.105
Number (no)	351
Page	pp.pp.-
#Pages	5
Date of Issue