Presentation 2005-10-20
Four-Pixel accuracy Motion Estimation Unit using Multiple Extended Templates for HDTV Encoding
Jin KOBAYASHI, Takahiro HIRAMATSU, Takahiro SASAKI, Toshio KONDO,
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Abstract(in English) This paper describes the design of a first-stage motion estimation unit using different extended templates for the hierarchical HDTV(1080p) motion estimator. The designed unit is composed of a 256-parallel PE array part, a partial sum part for the extended template SAD calculation and a compare part for detection of the minimum SAD. The main feature is the parallel search structure simultaneously executing 8×8 block matching in order to avoid recalculation of partial block SADs. The motion estimation unit has been designed up to mask pattern layout by using 0.18μm five-layer metal CMOS technology. As a result, we obtained the area size of 2.030×2.200mm^2 and the power consumption of 348mW at a 125MHz clock frequency and at a 1.8V supply voltage.
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Keyword(in English) HDTV / MPEG2 / Motion Estimation / Power Consumption / 1080p
Paper # SIP2005-106,ICD2005-125,IE2005-70
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Conference Date 2005/10/13(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Four-Pixel accuracy Motion Estimation Unit using Multiple Extended Templates for HDTV Encoding
Sub Title (in English)
Keyword(1) HDTV
Keyword(2) MPEG2
Keyword(3) Motion Estimation
Keyword(4) Power Consumption
Keyword(5) 1080p
1st Author's Name Jin KOBAYASHI
1st Author's Affiliation Graduate School of Engineering, Mie University()
2nd Author's Name Takahiro HIRAMATSU
2nd Author's Affiliation Graduate School of Engineering, Mie University
3rd Author's Name Takahiro SASAKI
3rd Author's Affiliation Faculty of Engineering, Mie University
4th Author's Name Toshio KONDO
4th Author's Affiliation Faculty of Engineering, Mie University
Date 2005-10-20
Paper # SIP2005-106,ICD2005-125,IE2005-70
Volume (vol) vol.105
Number (no) 351
Page pp.pp.-
#Pages 6
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