| Presentation | 2005-10-20 An Ultra-low Complexity Motion Estimation Algorithm and its Implementation of Specific Processor Seiichiro HIRATSUKA, Satoshi GOTO, Takeshi Ikenaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we propose an ultra-low complexity ME algorithm with adaptive block sub-sampling and several techniques. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose the implementation of the application specific instruction-set processor (ASIP). It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | motion estimation / full search / SAD / application specific instruction-set processor |
| Paper # | SIP2005-103,ICD2005-122,IE2005-67 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/10/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Ultra-low Complexity Motion Estimation Algorithm and its Implementation of Specific Processor |
| Sub Title (in English) | |
| Keyword(1) | motion estimation |
| Keyword(2) | full search |
| Keyword(3) | SAD |
| Keyword(4) | application specific instruction-set processor |
| 1st Author's Name | Seiichiro HIRATSUKA |
| 1st Author's Affiliation | Fukuoka Industry, Science & Technology Foundation:Kyushu Laboratory, Advanced Research Institute for Science & Engineering, Waseda University() |
| 2nd Author's Name | Satoshi GOTO |
| 2nd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University:Kyushu Laboratory, Advanced Research Institute for Science & Engineering, Waseda University |
| 3rd Author's Name | Takeshi Ikenaga |
| 3rd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University:Kyushu Laboratory, Advanced Research Institute for Science & Engineering, Waseda University |
| Date | 2005-10-20 |
| Paper # | SIP2005-103,ICD2005-122,IE2005-67 |
| Volume (vol) | vol.105 |
| Number (no) | 351 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |