Presentation 2005-07-29
Single-chip Implementation Sample of Received Signal Generator and MLD for Real Time Demonstration of MIMO Signal Processing Technique
Toshiaki KOIKE, Hidekazu MURATA, Susumu YOSHIDA, Kiyomichi ARAKI,
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Abstract(in English) We developed a maximum-likelihood detector (MLD) for multiple-input multiple-output (MIMO) systems, using a field programmable gate array (FPGA) device. For practical implementation, we introduce a simplified metric : referred to as a correlation metric. The correlation metric reduces the MLD complexity in multiplications from exponential order to cubic order according to the number of antennas, more remarkably without any performance degradation. The MLD prototype using the correlation metric has data processing capability over 1.3Gbps. In addition to the MLD prototype, we also implemented a 4×4 MIMO received signal generator on the same FPGA chip, for real time demonstration.
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Keyword(in English) FPGA / MLD / MIMO / Spatial multiplexing
Paper # SR2005-29
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Conference Date 2005/7/21(1days)
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Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Single-chip Implementation Sample of Received Signal Generator and MLD for Real Time Demonstration of MIMO Signal Processing Technique
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) MLD
Keyword(3) MIMO
Keyword(4) Spatial multiplexing
1st Author's Name Toshiaki KOIKE
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Hidekazu MURATA
2nd Author's Affiliation Graduate School of Science and Engineering, Tokyo Institute of Technology
3rd Author's Name Susumu YOSHIDA
3rd Author's Affiliation Graduate School of Informatics, Kyoto University
4th Author's Name Kiyomichi ARAKI
4th Author's Affiliation Graduate School of Science and Engineering, Tokyo Institute of Technology
Date 2005-07-29
Paper # SR2005-29
Volume (vol) vol.105
Number (no) 217
Page pp.pp.-
#Pages 7
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