Presentation 2002/8/15
Dependable Pipelining : Microarchitecture for the Multi-GHz Generation
Tsuyoshi MATSUO, Takuya FUJIKAWA, Katsuhiko METSUGI, Kazuaki MURAKAMI,
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Abstract(in English) The problem that the dominant factor determining the circuit delay is moving from the switching delay of transistors to the signal propagation delay on wires will come up. In this paper, as one of such future microarchitectures, we propose a pipeline design methodology, called Dependable Pipelining, which allows us to reduce the clock cycle time without increasing the pipeline depth, and therefore, to decrease the pipeline latency without compromising the pipeline throughput. In order to evaluate the performance of the dependable pipelined processor, we make a performance model. In addition, we explored the distribution of the delay time at the 32-bit Carry Look-ahead Adder. As a result, the effectiveness of the Dependable Pipelining could be found in an EX stage.
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Keyword(in English) Dependable Pipelining / Performance Modeling / Carry Look-ahead Adder
Paper # DC2002-20
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Conference Date 2002/8/15(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dependable Pipelining : Microarchitecture for the Multi-GHz Generation
Sub Title (in English)
Keyword(1) Dependable Pipelining
Keyword(2) Performance Modeling
Keyword(3) Carry Look-ahead Adder
1st Author's Name Tsuyoshi MATSUO
1st Author's Affiliation Department of Informatics, Kyushu University()
2nd Author's Name Takuya FUJIKAWA
2nd Author's Affiliation Department of Electrical Engineering & Computer Science, Kyushu University
3rd Author's Name Katsuhiko METSUGI
3rd Author's Affiliation Department of Informatics, Kyushu University
4th Author's Name Kazuaki MURAKAMI
4th Author's Affiliation Division of Informatics, Kyushu University
Date 2002/8/15
Paper # DC2002-20
Volume (vol) vol.102
Number (no) 262
Page pp.pp.-
#Pages 6
Date of Issue