Presentation 2005-09-16
Programmable Numerical Function Generators : Architectures and Synthesis Method
Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER,
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Abstract(in English) This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture partitions a given domain of function into non-uniform segments using an LUT(Look-Up Table) cascade, and approximates the given function by a linear polynomail for each segment. Thus, our architecture can implement fast and compact NFGs for a wide range of functions. We have developed a synthesis system for NFGs that converts MATLAB-like specification into HDL code. We show and compare three architectures implemented as a FPGA(Field-Programmable Gate Array). Experimental results show the efficiency of our architecture and synthesis system.
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Keyword(in English) LUT cascades / numerical function generators / pipeline processing / automatic synthesis / FPGA
Paper # RECONF2005-41
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Committee RECONF
Conference Date 2005/9/9(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Programmable Numerical Function Generators : Architectures and Synthesis Method
Sub Title (in English)
Keyword(1) LUT cascades
Keyword(2) numerical function generators
Keyword(3) pipeline processing
Keyword(4) automatic synthesis
Keyword(5) FPGA
1st Author's Name Shinobu NAGAYAMA
1st Author's Affiliation Department of Computer Engineering, Hiroshima City University()
2nd Author's Name Tsutomu SASAO
2nd Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology
3rd Author's Name Jon T. BUTLER
3rd Author's Affiliation Department of Electrical and Computer Engineering, Naval Postgraduate School
Date 2005-09-16
Paper # RECONF2005-41
Volume (vol) vol.105
Number (no) 288
Page pp.pp.-
#Pages 6
Date of Issue