Presentation 2005-09-15
On LUT Cascade Realizations of FIR Filters Using Arithmetic Decomposition
Tsutomu SASAO, Yukihiro IGUCHI, Takahiro SUZUKI,
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Abstract(in English) This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.
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Keyword(in English) Digital filter / Distributed arithmetic / LUT cascade / Functional decomposition / Binary decision diagram / FPGA
Paper # RECONF2005-33
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Committee RECONF
Conference Date 2005/9/8(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On LUT Cascade Realizations of FIR Filters Using Arithmetic Decomposition
Sub Title (in English)
Keyword(1) Digital filter
Keyword(2) Distributed arithmetic
Keyword(3) LUT cascade
Keyword(4) Functional decomposition
Keyword(5) Binary decision diagram
Keyword(6) FPGA
1st Author's Name Tsutomu SASAO
1st Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology()
2nd Author's Name Yukihiro IGUCHI
2nd Author's Affiliation Department of Computer Science, Meiji University
3rd Author's Name Takahiro SUZUKI
3rd Author's Affiliation Department of Computer Science, Meiji University
Date 2005-09-15
Paper # RECONF2005-33
Volume (vol) vol.105
Number (no) 287
Page pp.pp.-
#Pages 6
Date of Issue