| Presentation | 2005-09-15 Place and Route Processing in Back End Compiler for Reconfigurable Architecture 'PARS' Ryuji HADA, Takeshi FUKUDA, Kazuya TANIGAWA, Akira KOJIMA, Tetsuo HIRONAKA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A compiler of dynamic reconfigurable architecture with ability of highly parallel processing is required to extract parallelism in program as much as possible. In addition, it is also to realize an efficient place and route method to utilize much hardware resources. In our laboratory, we have developed PARS Back-End Compiler (P-BEC) as one of such a compiler. In a development of place and route process, we face a situation to be impossible to do this process, because of shortage of the number of registers and routing resources. To resolve the situation, our place and route process adds several codes to avoid the situation into target program. However, the addition of these codes causes decrease of the parallelism in target program. So we can say that it can't utilize a potential of target architecture enough. Therefore, in this paper, we propose a novel place and route process. This process realizes a reduction of code added in the above situation and more flexibility in replace process by simultaneous place and route process per operation. By introducing proposal place and route process, we achieve 152% higher performance than the traditional one in maximum. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable architecture / compiler / P-BEC / place and route |
| Paper # | RECONF2005-30 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2005/9/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Place and Route Processing in Back End Compiler for Reconfigurable Architecture 'PARS' |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable architecture |
| Keyword(2) | compiler |
| Keyword(3) | P-BEC |
| Keyword(4) | place and route |
| 1st Author's Name | Ryuji HADA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Takeshi FUKUDA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Kazuya TANIGAWA |
| 3rd Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
| 4th Author's Name | Akira KOJIMA |
| 4th Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
| 5th Author's Name | Tetsuo HIRONAKA |
| 5th Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
| Date | 2005-09-15 |
| Paper # | RECONF2005-30 |
| Volume (vol) | vol.105 |
| Number (no) | 287 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |