Presentation | 2005-05-13 The template reconfiguration for dynamically reconfigurable processors Masayasu SUZUKI, Hideharu AMANO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Dynamically reconfigurable processors improve the area-efficiency by executing a task over multiple hardware contexts. For complicated problems, a large number of hardware contexts are required, and the cost for configuration memory often becomes large although the utilization ratio is small. The template reconfiguration method can reduce the total amount of configuration memory by distributing the context allocation table into each processing element and sharing the same configuration data with multiple contexts. The evaluation result using a model based on NEC Electronics' DRP-1 shows that 75% of contexts can be reduced in the best case. Finally, the template reconfiguration, which builds configuration data from common templates and individual modifiers, is proposed for further improvement. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Reconfigurable Processor / DRP / Dynamic Reconfiguration |
Paper # | RECONF2005-24 |
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Committee | RECONF |
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Conference Date | 2005/5/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | The template reconfiguration for dynamically reconfigurable processors |
Sub Title (in English) | |
Keyword(1) | Reconfigurable Processor |
Keyword(2) | DRP |
Keyword(3) | Dynamic Reconfiguration |
1st Author's Name | Masayasu SUZUKI |
1st Author's Affiliation | Dept. of ICS, Keio University() |
2nd Author's Name | Hideharu AMANO |
2nd Author's Affiliation | Dept. of ICS, Keio University |
Date | 2005-05-13 |
Paper # | RECONF2005-24 |
Volume (vol) | vol.105 |
Number (no) | 43 |
Page | pp.pp.- |
#Pages | 6 |
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