Presentation 2005-05-13
An implementation of number-plate recognition algorithm on reconfigurable system
Takamasa KANAMORI, Shizuto FUKUDA, Yoshiaki AJIOKA, Masatoshi ARAI, Shinya HASHIMOTO, Hideharu AMANO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) An algorithm of recognition for car number plates is implemented on an FPGA-based acceleration board. Using the FPGA board, both sufficient performance for the frame rate and flexibility for the frequent improvement of the algorithm are achieved. The preliminary experimental results show that the performance is more than twice as that of the software on the common PC, and enough to process 30 frames per second.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Recognition / FPGA / Parallel Processing
Paper # RECONF2005-16
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Conference Information
Committee RECONF
Conference Date 2005/5/6(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An implementation of number-plate recognition algorithm on reconfigurable system
Sub Title (in English)
Keyword(1) Recognition
Keyword(2) FPGA
Keyword(3) Parallel Processing
1st Author's Name Takamasa KANAMORI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Shizuto FUKUDA
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Yoshiaki AJIOKA
3rd Author's Affiliation Ecchandes Inc.
4th Author's Name Masatoshi ARAI
4th Author's Affiliation CalsonicKansei Co.
5th Author's Name Shinya HASHIMOTO
5th Author's Affiliation Meitec Co.
6th Author's Name Hideharu AMANO
6th Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2005-05-13
Paper # RECONF2005-16
Volume (vol) vol.105
Number (no) 43
Page pp.pp.-
#Pages 5
Date of Issue