Presentation 2005-05-12
Reducing the Delay by Using the Small-World Network Structure
Hisashi TSUKIASHI, Masahiro IIDA, Toshinori SUEYOSHI,
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Abstract(in English) The logic density of FPGA has imploved rapidly. However, as for deep sub-micron processes, the wire delay accounts for a large share of entire delay. To resolve it, we have proposed a novel method applying the Small-World Network to FPGA routing structure. It adds a few random wires called Small-World line to regular routing structure. And so, it aims to reduce the wire delay. In this paper, we applied Small-World Network to routing structure with developed tool. Then, we evaluated our method using MCNC Benchmark circuits with modefied VPR corresponding to Small-World Network. As a result, critical path delay can be reduced by an average of 10%.
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Keyword(in English) FPGA / Wire delay / Routing Architecture / Small-World Network
Paper # RECONF2005-12
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Committee RECONF
Conference Date 2005/5/5(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reducing the Delay by Using the Small-World Network Structure
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Wire delay
Keyword(3) Routing Architecture
Keyword(4) Small-World Network
1st Author's Name Hisashi TSUKIASHI
1st Author's Affiliation Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University()
2nd Author's Name Masahiro IIDA
2nd Author's Affiliation The faculty of engineering, Kumamoto University:PRESTO, Japan Science and Technology Agency
3rd Author's Name Toshinori SUEYOSHI
3rd Author's Affiliation The faculty of engineering, Kumamoto University
Date 2005-05-12
Paper # RECONF2005-12
Volume (vol) vol.105
Number (no) 42
Page pp.pp.-
#Pages 6
Date of Issue