Presentation 2005-05-12
Implementation of an SMT Processor and its Reconfigurable Cache with FPGA
Yoshiyasu OGASAWARA, Norito KATO, Masanori YAMATO, Mikiko SATO, Koichi SASADA, Kaname UCHIKURA, Mitaro NAMIKI, Hironori NAKAJO,
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Abstract(in English) Recently, it becomes possible to implement a large-scale processor due to speed-up and large-scale integrity of an FPGA. Since cache of a multithreaded processor executes multiple threads, sharing rate of lines and optimal configuration are different for each program. In this paper, based on reconfiguration of cache, we have implemented an SMT processor in an FPGA with clock frequency of about 80MHz equipped with reconfigurable cache according to executed program. As a result, we have confirmed improvement of performance with increased hardware of about 1.3 times compared with a conventional superscalar processor. Moreover, we have found the optimal cache configurations for programs with our designed cache. And we have confirmed performance improvement with statically reconfigurable cache.
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Keyword(in English) FPGA / SMT / cache / reconfigurable architecture
Paper # RECONF2005-4
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Conference Information
Committee RECONF
Conference Date 2005/5/5(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of an SMT Processor and its Reconfigurable Cache with FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) SMT
Keyword(3) cache
Keyword(4) reconfigurable architecture
1st Author's Name Yoshiyasu OGASAWARA
1st Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology()
2nd Author's Name Norito KATO
2nd Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology:(Present address)Sony Corporation
3rd Author's Name Masanori YAMATO
3rd Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology:(Present address)TOSHIBA Corporation
4th Author's Name Mikiko SATO
4th Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology
5th Author's Name Koichi SASADA
5th Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology
6th Author's Name Kaname UCHIKURA
6th Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology
7th Author's Name Mitaro NAMIKI
7th Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology
8th Author's Name Hironori NAKAJO
8th Author's Affiliation Graduate School of Technology, Tokyo University of Agriculture and Technology
Date 2005-05-12
Paper # RECONF2005-4
Volume (vol) vol.105
Number (no) 42
Page pp.pp.-
#Pages 6
Date of Issue