| Presentation | 2005-05-12 Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure Ittetsu TANIGUCHI, Kyoko UEDA, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The dynamic reconfigurable processor is a device that can change interconnections between processor elements and processor elements' functions very quickly at run time. When using a dynamic reconfigurable processor, designers must consider division of processes into some configuration units. In this paper, we propose an execution cycle minimization algorithm for dynamic reconfigurable processor with hierarchical memory structure. Experimental results show that the proposed algorithm can detect the optimal solution for the target dynamic reconfigurable architecture with hierarchical memory structure. With the proposed algorithm, designers can easily evaluate the performance of various architectures for the specific application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamic Reconfigurable Processor / Hierarchical Memory Structure / Scheduling |
| Paper # | RECONF2005-3 |
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| Committee | RECONF |
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| Conference Date | 2005/5/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure |
| Sub Title (in English) | |
| Keyword(1) | Dynamic Reconfigurable Processor |
| Keyword(2) | Hierarchical Memory Structure |
| Keyword(3) | Scheduling |
| 1st Author's Name | Ittetsu TANIGUCHI |
| 1st Author's Affiliation | Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Kyoko UEDA |
| 2nd Author's Affiliation | Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Keishi SAKANUSHI |
| 3rd Author's Affiliation | Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University |
| 4th Author's Name | Yoshinori TAKEUCHI |
| 4th Author's Affiliation | Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University |
| 5th Author's Name | Masaharu IMAI |
| 5th Author's Affiliation | Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University |
| Date | 2005-05-12 |
| Paper # | RECONF2005-3 |
| Volume (vol) | vol.105 |
| Number (no) | 42 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |