Presentation 2005-05-12
Development of clustering tool to reduce area of chip and delay
Masaki KOBATA, Masahiro IIDA, Toshinori SUEYOSHI,
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Abstract(in English) In this paper, we present a clustering technique for area and delay reduction in clustered FPGAs. This technique uses two evaluation functions to optimize all wiring resources in a FPGA chip. One evaluation function is criterion we proposed in order to reduce wiring resources in the outside of the cluster before. So we adopt other criterion to reduce wireing resources in the inside of the cluster. We propose a clustering technique that has the ability to optimize all wiring resources in a FPGA chip concurrently. As a result, the area decreased by 40% (19% on avareage), and the delay reduced by 16% (2% on avareage).
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Keyword(in English) Clustering / Wire Delay / Cluster-based FPGA / Routing Resource
Paper # RECONF2005-2
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Committee RECONF
Conference Date 2005/5/5(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of clustering tool to reduce area of chip and delay
Sub Title (in English)
Keyword(1) Clustering
Keyword(2) Wire Delay
Keyword(3) Cluster-based FPGA
Keyword(4) Routing Resource
1st Author's Name Masaki KOBATA
1st Author's Affiliation Department of Mathematics and Computer Science, Graduate School of Science and Technology, Kumamoto University()
2nd Author's Name Masahiro IIDA
2nd Author's Affiliation The faculty of engineering, Kumamoto University:PRESTO, Japan Science and Technology Agency
3rd Author's Name Toshinori SUEYOSHI
3rd Author's Affiliation The faculty of engineering, Kumamoto University
Date 2005-05-12
Paper # RECONF2005-2
Volume (vol) vol.105
Number (no) 42
Page pp.pp.-
#Pages 6
Date of Issue