Presentation	2005-12-16 Low-Power High-Speed 90-nm CMOS Clock Driver Suguru Nagayama, Tadayoshi Enomoto,
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Abstract(in English)	A technique, which can minimize not only an active power (P_) and an stand-by power (P_) but also a delay time (t_d) of the CMOS clock driver, has been developed. The CMOS clock driver test circuits, each of which consists of a single inverter pre-driver stage, an m-parallel inverter driver stage-1 (m=1～40), an m-parallel inverter driver stage-2 and a resistor array stage consisting of M(=40) delay flip flops, has been fabricated using a 90-nm CMOS process technology. An inverter in the driver stage drives n(=M/m) delay flip flops. Both SPICE calculated results and experimental results showed that the minimum P_, P_ and t_ were obtained at m of 8 to 10.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	clock driver / CMOS / active power / stand-by power / short-circuit current / delay-time
Paper #	ICD2005-194
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Conference Information
Committee	ICD
Conference Date	2005/12/9(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Low-Power High-Speed 90-nm CMOS Clock Driver
Sub Title (in English)
Keyword(1)	clock driver
Keyword(2)	CMOS
Keyword(3)	active power
Keyword(4)	stand-by power
Keyword(5)	short-circuit current
Keyword(6)	delay-time
1st Author's Name	Suguru Nagayama
1st Author's Affiliation	Graduate School of Science and Engineering, Chuo University()
2nd Author's Name	Tadayoshi Enomoto
2nd Author's Affiliation	Graduate School of Science and Engineering, Chuo University
Date	2005-12-16
Paper #	ICD2005-194
Volume (vol)	vol.105
Number (no)	476
Page	pp.pp.-
#Pages	6
Date of Issue