| Presentation | 2005/12/14 Dose Optimization of Lateral SiC MOSFETs with Multi-RESURF Structure Masato NOBORIO, Jun SUDA, Tsunenobu KIMOTO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Dose designing for SiC RESURF MOSFETs have been investigated by device simulation and fabrication. The simulated MOSFETs, which are called double RESURF MOSFETs, have the low-doped n-type region near drain region (RESURF region) and the buried-p region inside the RESURF region. Since the RESURF region is depleted not only from the RESURF/p-epilayer interface but from the RESURF/buried-p interface, a higher RESURF dose can be employed than normal RESURF MOSFETs, leading to a lower on-resistance. The doses for double RESURF MOSFETs are optimized by device simulation. From the simulation results, the breakdown voltage was mainly determined by neither the RESURF dose nor buried-p dose itself but by the net RESURF dose. The authors have fabricated SiC double RESURF MOSFETs with the optimum dose. The fabricated double RESURF MOSFET exhibits a low on-resistance of 52mΩcm^2 and a high breakdown voltage of 750V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SiC / MOSFET / RESURF / device simulation / power device |
| Paper # | SDM2005-223 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2005/12/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dose Optimization of Lateral SiC MOSFETs with Multi-RESURF Structure |
| Sub Title (in English) | |
| Keyword(1) | SiC |
| Keyword(2) | MOSFET |
| Keyword(3) | RESURF |
| Keyword(4) | device simulation |
| Keyword(5) | power device |
| 1st Author's Name | Masato NOBORIO |
| 1st Author's Affiliation | Department of Electronic Science and Engineering, Kyoto University() |
| 2nd Author's Name | Jun SUDA |
| 2nd Author's Affiliation | Department of Electronic Science and Engineering, Kyoto University |
| 3rd Author's Name | Tsunenobu KIMOTO |
| 3rd Author's Affiliation | Department of Electronic Science and Engineering, Kyoto University |
| Date | 2005/12/14 |
| Paper # | SDM2005-223 |
| Volume (vol) | vol.105 |
| Number (no) | 492 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |