| Presentation | 1999/9/22 An Approach to Reconfigurable Hardware-based Cryptosystems Zaldy ANDALES, Yukio MITSUYAMA, Koji ASARI, Takao ONOYE, Isao SHIRAKAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cryptosystem called Chameleon is proposed. The algorithm employs 8-context reconfigurable hardware units to generate different subkeys for each of the 16 half-rounds of its encryption/decryption process. The configuration context in each half-round changes based on information from the key. The scheme provides features with can increase the level of security for block ciphers. The proposed architecture has been implemented in 0.6 μm CMOS 3LM technology with a core size of 3.19×3.19 mm^2 containing 153,147 transistors. Running on a 100 MHz clock, a data throughput of 400 Mbps was attained. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic / encryption / cipher / VLSI |
| Paper # | NLP99-87 |
| Date of Issue |
| Conference Information | |
| Committee | NLP |
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| Conference Date | 1999/9/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Reconfigurable Hardware-based Cryptosystems |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic |
| Keyword(2) | encryption |
| Keyword(3) | cipher |
| Keyword(4) | VLSI |
| 1st Author's Name | Zaldy ANDALES |
| 1st Author's Affiliation | Dept. Information Systems Eng., Osaka University() |
| 2nd Author's Name | Yukio MITSUYAMA |
| 2nd Author's Affiliation | Dept. Information Systems Eng., Osaka University |
| 3rd Author's Name | Koji ASARI |
| 3rd Author's Affiliation | Dept. Information Systems Eng., Osaka University:Semiconductor Company |
| 4th Author's Name | Takao ONOYE |
| 4th Author's Affiliation | Dept. Information Systems Eng., Osaka University |
| 5th Author's Name | Isao SHIRAKAWA |
| 5th Author's Affiliation | Dept. Information Systems Eng., Osaka University |
| Date | 1999/9/22 |
| Paper # | NLP99-87 |
| Volume (vol) | vol.99 |
| Number (no) | 324 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |