Presentation	1999/9/22 Array Cell Architecture for NMOS 4-Phase Dynamic Logic Makoto FURUIE, Bao-Yu SONG, Yukihiro YOSHIDA, Takao ONOYE, Isao SHIRAKAWA,
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Abstract(in English)	An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M×N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the NMOS 4-phase dynamic logic.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Array Cell / NMOS 4-phase / dynamic logic / low-power
Paper #	NLP99-86
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Conference Information
Committee	NLP
Conference Date	1999/9/22(1days)
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Paper Information
Registration To	Nonlinear Problems (NLP)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Array Cell Architecture for NMOS 4-Phase Dynamic Logic
Sub Title (in English)
Keyword(1)	Array Cell
Keyword(2)	NMOS 4-phase
Keyword(3)	dynamic logic
Keyword(4)	low-power
1st Author's Name	Makoto FURUIE
1st Author's Affiliation	Dept. Inf. Sys. Eng., Osaka Univ.()
2nd Author's Name	Bao-Yu SONG
2nd Author's Affiliation	Dept. Inf. Sys. Eng., Osaka Univ.
3rd Author's Name	Yukihiro YOSHIDA
3rd Author's Affiliation	Dept. Inf. Sys. Eng., Osaka Univ.
4th Author's Name	Takao ONOYE
4th Author's Affiliation	Dept. Inf. Sys. Eng., Osaka Univ.
5th Author's Name	Isao SHIRAKAWA
5th Author's Affiliation	Dept. Inf. Sys. Eng., Osaka Univ.
Date	1999/9/22
Paper #	NLP99-86
Volume (vol)	vol.99
Number (no)	324
Page	pp.pp.-
#Pages	6
Date of Issue