Presentation 1999/11/25
A Scalable Frame-Synchronization Circuit for super-parallel optical interconnections
Kimihiro YAMAKOSHI, Ryuusuke KAWANO, Naoaki YAMANAKA,
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Abstract(in English) A Scalable frame-synchronization circuit for super-parallel optical interconnections is presented. In general, Frame-synchronization is performed by counting for off-set clock cycles referred to the master channel and skew-compensation is performed based on the clock cycles. A conventional frame-synchronization circuit can not generate a frame-recognizing signal in a required speed and this prevents from counting the off-set clock cycles properly. A new circuit is composed of two parts; one that is required to operate at the clock speed same as the transmission rate and the other that does not need to operate at high speed. This architecture enables easily to increase the number of parallel channel without decreasing the transmission clock rate. The circuit for 622-Mb/s parallel optical transmission system is is simulated by HSPICE based on 0.25μm CMOS technology.
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Keyword(in English) parallel optical interconnection / frame synchronization / scalability
Paper # OCS99-85
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Conference Information
Committee OCS
Conference Date 1999/11/25(1days)
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Registration To Optical Communication Systems (OCS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Scalable Frame-Synchronization Circuit for super-parallel optical interconnections
Sub Title (in English)
Keyword(1) parallel optical interconnection
Keyword(2) frame synchronization
Keyword(3) scalability
1st Author's Name Kimihiro YAMAKOSHI
1st Author's Affiliation NTT Network Service Systems Laboratories()
2nd Author's Name Ryuusuke KAWANO
2nd Author's Affiliation NTT Electronics
3rd Author's Name Naoaki YAMANAKA
3rd Author's Affiliation NTT Network Service Systems Laboratories
Date 1999/11/25
Paper # OCS99-85
Volume (vol) vol.99
Number (no) 462
Page pp.pp.-
#Pages 6
Date of Issue