| Presentation | 1999/12/17 A Study on Convergence Condition in the PLL Frequency Synthesizer with Multi-PD Yasuaki SUMI, Hidekazu ISHII, Shigeki OBOTE, Naoki KITAI, Atsushi WATANABE, Hitoshi HORI, Yoshio ITOH, Yutaka FUKUI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Nowadays in the communication fields, Phase Locked Loop (PLL) frequency synthesizer used as a local oscillator will be more necessary to operate in a higher frequency region. And so the various methods are proposed in order to attain the fast lock-up time. The lock-up time depends on the gain of each block composed of the PLL. We have paid attention to the gain of programmable divider (PD), which is one of the important components. We have proposed multi-PD system, in order to the increase of PD's gain without using the fractional method. In addition, we have also proposed the control gate method changing the number of multi-stage PD's according to the operating mode. We call it turbo system. Although the reference frequency and the division ratio keep the same value, our proposal can achieve a more high-speed lock up time. In this method, we can use the conventional PLL technology and it makes easy to make LSI implementation. It operates at a single PD mode in a steady state, and does at a multi-PD one in a search mode. Therefore we can get the same characteristics as a conventional PLL. It is the most important from the view point of practical use. In this paper, we discuss the convergence conditions of a multi-PD mode to single PD mode by using the turbo control method indispensable to improve the power consumption and the basic characteristics of PLL system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PLL frequency synthesizer / high-speed lock up / Multi-PD method / programmable divider / Turbo controller |
| Paper # | DSP99-137 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1999/12/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Convergence Condition in the PLL Frequency Synthesizer with Multi-PD |
| Sub Title (in English) | |
| Keyword(1) | PLL frequency synthesizer |
| Keyword(2) | high-speed lock up |
| Keyword(3) | Multi-PD method |
| Keyword(4) | programmable divider |
| Keyword(5) | Turbo controller |
| 1st Author's Name | Yasuaki SUMI |
| 1st Author's Affiliation | Tottori SANYO Electric Co., Ltd.() |
| 2nd Author's Name | Hidekazu ISHII |
| 2nd Author's Affiliation | Faculty of Engineering, Tottori University |
| 3rd Author's Name | Shigeki OBOTE |
| 3rd Author's Affiliation | Faculty of Engineering, Tottori University |
| 4th Author's Name | Naoki KITAI |
| 4th Author's Affiliation | Faculty of Engineering, Tottori University |
| 5th Author's Name | Atsushi WATANABE |
| 5th Author's Affiliation | Faculty of Engineering, Tottori University |
| 6th Author's Name | Hitoshi HORI |
| 6th Author's Affiliation | Faculty of Engineering, Tottori University |
| 7th Author's Name | Yoshio ITOH |
| 7th Author's Affiliation | Faculty of Engineering, Tottori University |
| 8th Author's Name | Yutaka FUKUI |
| 8th Author's Affiliation | Faculty of Engineering, Tottori University |
| Date | 1999/12/17 |
| Paper # | DSP99-137 |
| Volume (vol) | vol.99 |
| Number (no) | 505 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |