Presentation 1999/10/29
MPEG2 MP@HL Decoder LSI for Digital TVs
Yasuhiro Watanabe, Hidenaga Takahashi, Koji Yoshitomi, Yukio Otobe, Kiyoshi Kohiyama,
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Abstract(in English) We developed MPEG2 decoder LSI for digital TVs. It integrated TS decoding, MPEG2 video decoding, format conversion and other functions on a single chip. This LSI guarantees proper decoding of MPEG2 MP@HL for worst-case streams by using the fixed-period-based memory access control, and realizes simultaneous decoding of multiple MP@ML with the time-sharing technique. It also realizes the seamless decoding when the source size or frame rate changed and error concealment techniques using the architecture based on synchronizing decoding and display processes.
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Keyword(in English) MPEG / MP@HL / LSI / multiple decoding / seamless decoding / error concealment
Paper # DSP99-107
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Conference Information
Committee DSP
Conference Date 1999/10/29(1days)
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Paper Information
Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) MPEG2 MP@HL Decoder LSI for Digital TVs
Sub Title (in English)
Keyword(1) MPEG
Keyword(2) MP@HL
Keyword(3) LSI
Keyword(4) multiple decoding
Keyword(5) seamless decoding
Keyword(6) error concealment
1st Author's Name Yasuhiro Watanabe
1st Author's Affiliation Fujitsu Laboratories Ltd.()
2nd Author's Name Hidenaga Takahashi
2nd Author's Affiliation Fujitsu Laboratories Ltd.
3rd Author's Name Koji Yoshitomi
3rd Author's Affiliation Fujitsu Laboratories Ltd.
4th Author's Name Yukio Otobe
4th Author's Affiliation Fujitsu Laboratories Ltd.
5th Author's Name Kiyoshi Kohiyama
5th Author's Affiliation Fujitsu Laboratories Ltd.
Date 1999/10/29
Paper # DSP99-107
Volume (vol) vol.99
Number (no) 397
Page pp.pp.-
#Pages 8
Date of Issue