Presentation 1999/12/16
Delay Performance Evaluation of a Scalable Packet Switch
Hideaki Nakakita, Yoshimitsu Shimojo,
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Abstract(in English) We present a packet switch architecture suitable for Internet routers and ATM switches. This architecture is based on a multi-stage packet switch composed of bufferless unit switches, which is scalable for the number of port. We present as one of major features in the architecture, a congestion control algorithm between any ingress buffer and any egress buffer. This algorithm aims to prevent a certain port congestion from affecting traffic for any other ports. We evaluate our architecture with simulations. We examine packet transfer delay from buffer to egress buffer. Our simulation results show that in our architecture a certain port congestion does not influence traffic for any other ports.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Router / ATM Switch / Packet Switch / Congestion Control / Scalable and Simulation
Paper # SSE99-119
Date of Issue

Conference Information
Committee SSE
Conference Date 1999/12/16(1days)
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Paper Information
Registration To Switching Systems Engineering (SSE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Delay Performance Evaluation of a Scalable Packet Switch
Sub Title (in English)
Keyword(1) Router
Keyword(2) ATM Switch
Keyword(3) Packet Switch
Keyword(4) Congestion Control
Keyword(5) Scalable and Simulation
1st Author's Name Hideaki Nakakita
1st Author's Affiliation Communication Platform Laboratory, TOSHIBA Corporate Research & Development Center()
2nd Author's Name Yoshimitsu Shimojo
2nd Author's Affiliation Communication Platform Laboratory, TOSHIBA Corporate Research & Development Center
Date 1999/12/16
Paper # SSE99-119
Volume (vol) vol.99
Number (no) 506
Page pp.pp.-
#Pages 6
Date of Issue