| Presentation | 1999/11/27 Area/Delay Estimation Techniques for Digital Signal Processor Cores Yoshiharu KATAOKA, Dai YOSHIZAWA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A hardware/software cosynthesis system for digital signal processors with two types of register files requires to certain evalution values in the phase of hardware/software partitioning. These evaluation values are execution time of a given application program and a hardware cost of a generated processor core. In order to obtain these evaluation values, we, in advance, configure a variety of hardware units and the results are logic-synthesized and analyzed to establish estimation equations. We propose techniques for deriving the convincing equations which estimate both the delay and the area of the target processor core. For the area estimation, we show that the total area can be derived by the summation of area of a processor kernel and area of additional hardware units. The processor kernel area amounts to two independent rules: (1) area corresponding to an overhead when extra hardware units are added; (2) the size of general-purpose resisters. We have compared the derived estimation values with the in-advance logic-synthesized data. Errors of the area estimation are less than 2%. For the delay estimation, we can reduce estimation errors by focusing on the functional units on a critical path. Errors of the delay estimation are all less than 2ns. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware/software cosynthesis / hardware/software partitioning / processor core / area/delay estimation |
| Paper # | VLD99-75 |
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| Committee | VLD |
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| Conference Date | 1999/11/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area/Delay Estimation Techniques for Digital Signal Processor Cores |
| Sub Title (in English) | |
| Keyword(1) | hardware/software cosynthesis |
| Keyword(2) | hardware/software partitioning |
| Keyword(3) | processor core |
| Keyword(4) | area/delay estimation |
| 1st Author's Name | Yoshiharu KATAOKA |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University() |
| 2nd Author's Name | Dai YOSHIZAWA |
| 2nd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| Date | 1999/11/27 |
| Paper # | VLD99-75 |
| Volume (vol) | vol.99 |
| Number (no) | 475 |
| Page | pp.pp.- |
| #Pages | 8 |
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