Presentation 1999/12/2
A Split Level BUS for Low-Power High-Speed LSI's
Shoichiro Kawashima, Makoto Hamaminato, Isao Fukushi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A clocked-inverter is expanded as its pMOS and nMOS cascade nodes to be the two Split-level-BUS lines. Thus the BUS swings are reduced to VDD - |Vt|, which reduces the BUS driving power. A full VDD swing comes out at the receiver with no extra power consumption, and the charge transfer or the cascode scheme of the receiver eliminates a transient delay of the BUS. A 10 mm Split-level-BUS showed one third the power consumption at 1 V and half the propagation delay compared with a normal BUS structure.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) high-speed / low-power / charge-transfer-amplifier / small-swing-BUS / low-voltage
Paper # ICD99-218
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Conference Information
Committee ICD
Conference Date 1999/12/2(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Split Level BUS for Low-Power High-Speed LSI's
Sub Title (in English)
Keyword(1) high-speed
Keyword(2) low-power
Keyword(3) charge-transfer-amplifier
Keyword(4) small-swing-BUS
Keyword(5) low-voltage
1st Author's Name Shoichiro Kawashima
1st Author's Affiliation Fujitsu Laboratories Limited()
2nd Author's Name Makoto Hamaminato
2nd Author's Affiliation Fujitsu Laboratories Limited
3rd Author's Name Isao Fukushi
3rd Author's Affiliation Fujitsu Laboratories Limited
Date 1999/12/2
Paper # ICD99-218
Volume (vol) vol.99
Number (no) 485
Page pp.pp.-
#Pages 8
Date of Issue