| Presentation | 1999/12/2 Voltage Bounce Testing in Power Supply Lines Using Onchip-Voltage Scan Path Makoto IKEDA, Hideyuki AOKI, Kunihiro ASADA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an onchip-voltage scan path technique to monitor voltage bounce in power supply lines. Onchip-voltage scan path is consist of series connected voltage sampler with a regenerative comparator using a modified switched capacitor. We demonstrate that this technique can effectively monitor voltage bounce in power supply lines. A quality of power supply lines can be effectively enhanced when this technique is applied to a real chip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | On-chip voltage-scan path / supply voltage bounce / quality of power-line design / system-on-the-chip |
| Paper # | ICD99-217 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1999/12/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Voltage Bounce Testing in Power Supply Lines Using Onchip-Voltage Scan Path |
| Sub Title (in English) | |
| Keyword(1) | On-chip voltage-scan path |
| Keyword(2) | supply voltage bounce |
| Keyword(3) | quality of power-line design |
| Keyword(4) | system-on-the-chip |
| 1st Author's Name | Makoto IKEDA |
| 1st Author's Affiliation | VLSI Design and Education Center, University of Tokyo() |
| 2nd Author's Name | Hideyuki AOKI |
| 2nd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 3rd Author's Name | Kunihiro ASADA |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 1999/12/2 |
| Paper # | ICD99-217 |
| Volume (vol) | vol.99 |
| Number (no) | 485 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |