Presentation 1999/11/27
EVERY7SP-An Equivalence Checker for Transistor-Level Verification
Chiaki Arao, Shigeto Inui, Shuzo Murai, Kazuyuki Suganami,
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Abstract(in English) We have developed an equivalence checker for transistor-level-EVERY7SP. EVERY7SP verifies logic equivalence between transistor-level netlist and functional specification. By extracting such as latch-node and dynamic-node from netlist, this system can deal with F/F, latch and domino logic. It can also distinguish high-impedance and conflict, by using simulation-based approach instead of formal verification.
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Keyword(in English) transistor-level / equivalence check / domino
Paper # ICD99-212
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Conference Date 1999/11/27(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) EVERY7SP-An Equivalence Checker for Transistor-Level Verification
Sub Title (in English)
Keyword(1) transistor-level
Keyword(2) equivalence check
Keyword(3) domino
1st Author's Name Chiaki Arao
1st Author's Affiliation NEC Software Hokuriku, Ltd.()
2nd Author's Name Shigeto Inui
2nd Author's Affiliation NEC Silicon System Laboratories
3rd Author's Name Shuzo Murai
3rd Author's Affiliation NEC Computers Division
4th Author's Name Kazuyuki Suganami
4th Author's Affiliation NEC Software Hokuriku, Ltd.
Date 1999/11/27
Paper # ICD99-212
Volume (vol) vol.99
Number (no) 477
Page pp.pp.-
#Pages 8
Date of Issue