Presentation 1999/11/27
The Worst-case Delay Reduction Method for Repeater-inserted Bus Considering Crosstalk
Kei HIROSE, Hiroto YASUURA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) On-chip bus delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch for opposite transient directions. This paper proposes the delay reduction technique for a repeater-inserted on-chip bus by shifting signal transition timing of adjacent wires. The result of SPICE simulation shows that 5% to 20% reduction of the total bus delay can be achieved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Bus Line / Repeater / Crosstalk / Delay Reduction / LSI
Paper # ICD99-207
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Conference Date 1999/11/27(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The Worst-case Delay Reduction Method for Repeater-inserted Bus Considering Crosstalk
Sub Title (in English)
Keyword(1) Bus Line
Keyword(2) Repeater
Keyword(3) Crosstalk
Keyword(4) Delay Reduction
Keyword(5) LSI
1st Author's Name Kei HIROSE
1st Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University()
2nd Author's Name Hiroto YASUURA
2nd Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University
Date 1999/11/27
Paper # ICD99-207
Volume (vol) vol.99
Number (no) 477
Page pp.pp.-
#Pages 8
Date of Issue