Presentation 1999/10/29
A singple chip digital TV LSI with a flexible 2D graphic processor utilized optimizing memory architecture
Eiichiro Tomonaga, Masahiro Yamada,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We developed a single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory. This LSI has dedicated RISC processor for graphic processing, it manages three devices using multi task scheme. These three tasks correspond to three control blocks as display, video capturing and BitBlt. In this LSI, we have tried to share a host and graphics memories, as to reduce memory cost and improve graphics performance without data transmit between those memories. However, this method has a problem of memory bandwidth. We solve this problem to introduce plural layer of memory arbitration and to change memory access priorities of DMA controllers and CPU.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) digital TV / graphic / unified memory / memory arbitration
Paper # ICD99-195
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Conference Date 1999/10/29(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A singple chip digital TV LSI with a flexible 2D graphic processor utilized optimizing memory architecture
Sub Title (in English)
Keyword(1) digital TV
Keyword(2) graphic
Keyword(3) unified memory
Keyword(4) memory arbitration
1st Author's Name Eiichiro Tomonaga
1st Author's Affiliation Toshiba corporation Digital Media Equipment & Services company()
2nd Author's Name Masahiro Yamada
2nd Author's Affiliation Toshiba corporation Digital Media Equipment & Services company
Date 1999/10/29
Paper # ICD99-195
Volume (vol) vol.99
Number (no) 399
Page pp.pp.-
#Pages 4
Date of Issue